1. Field of the Invention
The present invention relates to a method of forming a nonvolatile memory, and more particularly, to a method of forming a split-gate flash memory.
2. Description of the Prior Art
Nonvolatile memories have the advantages of maintaining stored data while the power supply is interrupted, and thus have been widely employed in recent years. According to the bit numbers stored by a single memory cell, nonvolatile memories are divided into single-bit storage nonvolatile memories, including nitride-based non-volatile memories such as Nitride Read-Only-Memory (NROM), Metal-Oxide-Nitride-Oxide-Silicon (MONOS) memories or Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memories, and dual-bit storage nonvolatile memories, such as split-gate SONOS memories and split-gate MONOS memories. Comparing to the traditional single-bit storage memories, the split-gate SONOS memories and split-gate MONOS memories are capable of storing more data, and thus have gradually become more and more popular in the memory device market.
Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are schematic diagrams of a split-gate SONOS memory 10, where FIG. 1 illustrates the split-gate SONOS memory 10 during a programming operation, and FIG. 2 illustrates the split-gate SONOS memory 10 during an erasing operation. It is appreciated that only a single memory cell is illustrated in FIG. 1 and FIG. 2 for clearly demonstrating the structure and operational theorem of the split-gate SONOS memory 10. As shown in FIG. 1, the split-gate SONOS memory 10 is formed on a P well 12, which includes a select gate 14, and two N buried bit lines, respectively serving as a source 16 and a drain 18, positioned on the opposite sides of the P well 12. The split-gate SONOS memory 10 further includes a gate insulating layer 20 between the select gate 14 and the P well 12, and a cap layer 22 above the select gate 14. In addition, the split-gate SONOS memory 10 further includes a bottom silicon oxide layer 24, a silicon nitride layer 26, and a top silicon oxide layer 28 on the select gate 14 and the P well 12. The silicon nitride layer 26 works as a storage medium for trapping electrons or hot holes. Furthermore, the split-gate SONOS memory 10 has a word line 30 positioned on the top silicon oxide layer 28.
As shown in FIG. 1, the split-gate SONOS memory 10 is programmed by a source-side injection mechanism. The voltage operations are as follows: the world line 30 is applied with a high positive voltage (e.g. 6 to 9V); the select gate 14 is applied with a low positive voltage (e.g. 1V); the source 18 is applied with a positive voltage (e.g. 4.5V); and the P well 12 and the drain 16 are maintained at 0V. Under these voltage operations, electrons which traverse the channel underneath the select gate 14 will be captured and trapped in the silicon nitride layer 26 close to the source 18 (as the arrow marks show in FIG. 1) to store a bit of data. In addition, under similar inverse voltage operations, electrons can be trapped in the silicon nitride layer 26 close to the drain 16 to store another bit of data.
As shown in FIG. 2, the split-gate SONOS memory 10 is erased by a band-to-band hot hole injection mechanism. The voltage operations are as follows: the world line 30 is applied with a high negative voltage (e.g. −6 to −9V); the source 18 is applied with a positive voltage (e.g. 4.5V); the select gate 14 is maintained at a level lower than the threshold voltage, and the P well 12 and the drain 16 are maintained at 0V. Under these voltage operations, hot holes in the P well 12 will inject to the silicon nitride layer 26 close to the source 18, and neutralize the electrons trapped in the silicon nitride layer 26. Similarly, the electrons trapped in the silicon nitride layer 26 close to the drain 16 can be neutralized under similar inverse voltage operations.
Please refer to FIG. 3 to FIG. 6. FIG. 3 to FIG. 6 are schematic diagrams illustrating a conventional method of forming a split-gate SONOS memory. For easy illustration, only parts of memory cells are shown. As shown in FIG. 3, a substrate 50 including a P well 52 is formed, and a plurality of select gate structures 54 are positioned on the P well 52. Each select gate structure 54 from bottom to top includes a gate insulating layer 56, a select gate 58, and a cap layer 60. The gate insulating layer 56 is a silicon oxide layer formed by a thermal oxidization process or a deposition process, the select gate 58 is a polysilicon layer, and the cap layer 60 is a silicon nitride layer or a polycide.
As shown in FIG. 4, a composite dielectric layer (ONO tri-layer dielectric) 62 including a bottom silicon oxide layer 64, a silicon nitride layer 66, and a top silicon oxide layer 68 are formed on the substrate 50 and the select gate structures 54. Thereafter, a silicon oxide layer 70 is deposited as sacrificial spacers to be formed later.
As shown in FIG. 5, an etching back process is performed to entirely etch back the silicon oxide layer 70 for forming sacrificial spacers 72 alongside each select gate structure 54. The etching back process is not stopped until the composite dielectric layer 62 is open so as to form an opening 74 between any two adjacent sacrificial spacers 72. Thereafter, an implantation process is performed to form a plurality of N doped regions 76, which serve as buried bit lines, in the P well 52 via the openings 74. Afterward, an insulating layer (not shown) is entirely deposited on the top silicon oxide layer 68 and on the N doped regions 76, and an etching back process is performed to form a blocking film 78 on each N doped region 76.
As shown in FIG. 6, an etching process is then performed to remove the sacrificial spacers 72. A polysilicon layer 80 is totally deposited, and a photolithography and etching process is performed to define word lines 80.
As described, the process for forming the N doped regions 76 is performed after forming the composite dielectric layer 62 according to the conventional method. In other words, the composite dielectric layer 62 between any two adjacent sacrificial spacers 72 must be removed before forming the N doped regions 76. In addition, the blocking film 78 has to be formed before forming the word lines 80, or alternatively another silicon oxide layer (not shown) has to be formed after removing the sacrificial spacers 76 to avoid short circuits between the word lines 80 and the N doped regions (buried bit lines) 76. It is appreciated that even though the short circuit problem is avoided by forming the blocking film 78, other factors, such as the incompletion of the composite dielectric layer 62, the remaining etching stress, and the etching infirmity, may cause damage to the split-gate SONOS memory. For example, a higher voltage difference between the word lines and the buried bit lines may be necessary when performing the erasing operation, or a current leakage problem may occur. This leads to tunneling between the word lines and the buried bit lines, and reduces the reliability of split-gate SONOS memory.
Therefore, the manufacturing process for split-gate flash memories still needs improvement to enhance the reliability of split-gate flash memory and the yield for production.